1. Field of the Invention
The present invention relates to semiconductor integrated circuit memory arrays, and particularly those incorporating write-once passive element memory cells incorporating anti-fuses.
2. Description of the Related Art
Manufacturers of integrated circuits that include write-once memory arrays (also known as one-time programmable, or OTP memory arrays), particularly those incorporating anti-fuse memory cells, face difficult testing problems. One such problem concerns testing each unprogrammed memory cell, for it is desirable to test each memory cell to ensure that the unprogrammed state (e.g., high-impedance state) exists at every memory cell location. A standard read mode test can be employed to ensure this. However, the test time required to perform such a read mode test of every memory cell is significant, especially in a very large array such as a three dimensional memory array having upwards of a billion memory cells. Such long test times contribute to increased product manufacturing cost.
With the increasing size of commercially viable memory devices, there remains a continued need for improved and lower cost testing techniques.
Multiple memory cells on a single bit line may be tested in parallel for the unprogrammed state by simultaneously selecting multiple word lines associated with a selected bit line within a sub-array. A read current flowing through each selected memory cell is added on the selected bit line, thus logically performing an OR function of any selected memory cell found to be in the programmed state. The total read current through one or more selected memory cells onto the selected bit line may be sensed using the same bit line sense circuits used for normal read operations. Separate sense amplifiers may also be used, but are not required, nor is any complicated BIST (i.e., built-in-self-test) logic.
The word line decoding circuitry preferably responds to a test mode signal to cause more than one word line to be selected in the test mode. In an exemplary embodiment, the test mode signal causes a portion of the row address signals to be ignored, which allows more than one word line to be selected. Preferably the ignored address signals represent low-order row address signals and consequently the multiply selected word lines are all adjacent to each other in a contiguous block within a sub-array. Exemplary numbers of simultaneously selected world lines include 4, 8, 16, 32, or 64 word lines, with 16 such simultaneously selected word lines being particularly preferred.
A sense circuit is preferably coupled to the selected bit line and generates a read signal which, in the test mode, indicates a pass/fail condition for all N simultaneously selected memory cells. Such a pass/fail indication may be directly conveyed as an output signal of the integrated circuit, or may be combined with other similar pass/fail signals from other selected bit line sense circuits to generate a combined pass/fail signal representing an even greater number of simultaneously tested memory cells which is then conveyed as an output signal. Multiple bit lines may be simultaneously selected within the same sub-array to each generate a multiple respective pass/fail signals which are then combined into fewer numbers of output signals. In addition, multiple sub-arrays may be simultaneously selected, each having one or more simultaneously selected bit lines, and the respective pass/fail signals conveyed directly or combined into fewer numbers of such signals, including just one such combined pass/fail signal. In certain embodiments, the pass/fail signals may be generated to also indicate a third (e.g., xe2x80x98marginalxe2x80x99) condition, upon which additional and/or more thorough testing may be initiated for the affected memory cells.
The invention may be advantageously applied to parallel testing of memory cells which have a low-current and a high-current state and which contribute such current, when selected, onto an associated bit line. It is particularly useful for testing passive element memory cells to ensure that each memory cell remains in its low current state. Passive element memory cells having anti-fuse elements may be tested in parallel to ensure that each remains in its unprogrammed (i.e., high impedance) state or that no other manufacturing defects are present which contribute current flow onto a selected bit line. The invention is particularly well-suited to three-dimensional memory arrays (i.e., having more than one plane of memory cells) incorporating anti-fuse passive element memory cells. In some embodiments, word lines from each of two layers that are both associated with a single bit line layer may be simultaneously selected to test in parallel memory cells located in two adjacent memory planes.